1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of fabricating the same, and more particularly to forming of a superhigh speed bipolar transistor of self-aligned type and an IIL device on the same semiconductor substrate.
2. Description of the Prior Art
It is easy to integrate high speed ECL (emitter-coupled logic) circuit, analog circuit, and other bipolar circuit on a same chip. Accordingly, IIL (integrated injection logic) devices are widely used in an integrated circuit in which digital circuits and analog circuits coexist.
A circuit diagram of an IIL device is shown in FIG. 3.
The vertical transistor composing the IIL device is different from an ordinary vertical transistor because the carrier moves in the reverse direction. In the ordinary vertical transistor, the emitter, base and collector are disposed sequentially from the diffusion layer of high concentration close to the surface. By contrast, in the vertical transistor of IIL device, the collector, base and emitter are disposed in this order from the diffusion layer of high concentration close to the surface. In other words, the vertical transistor of IIL device possesses a reverse direction structure as compared with the ordinary vertical transistor. The IIL device is a logic device composed of a vertical NPN transistor 1 having such reverse direction structure, and a lateral PNP transistor 2.
The lateral PNP transistor 2 has a complex structure using the base of the vertical NPN transistor 1 of reverse direction structure as its collector. Here, the PNP transistor 2 functions as an injector 3 for injecting holes to the base of the NPN transistor 1. On the other hand, the vertical NPN transistor 1 functions as an inverter.
Recent bipolar transistors are meanwhile, made finer and smaller by employing the self-aligned technology, and a high speed ECL circuit may be realized, as disclosed in the Japanese Patent Publication Hei. 2-108451. This disclosure is explained below while referring to drawings.
FIG. 4 (a) to (d) are process sequence sectional views for explaining the manufacturing method of NPN bipolar transistor employing the conventional self-aligned technology.
A buried collector layer 12 is formed on the surface of a silicon substrate 11. Later, an epitaxial layer 13 is grown on the buried collector layer 12. Consequently, a LOCOS film 14 for electrical isolation is formed in a specified region on the surface of the buried collector layer 12. Afterwards, a polysilicon film as a base leading-out electrode 15 and then an oxide film 16 are grown on the entire surface. Furthermore, by ion implantation, boron as an impurity is implanted into the polysilicon film which is used as the base leading-out electrode 15. Using the resist employed in the photolithography as the mask, the oxide film 16 and the polysilicon film as base leading-out electrode 15 are selectively removed by etching. In this way, an intrinsic base region 17 is exposed on the surface of the epitaxial layer 13 (FIG. 4 (a)).
Next, a nitride film 18 is grown on the oxide film 16 and intrinsic base region 17. Then, by heat treatment, the boron is introduced into the peripheral part of the intrinsic base region 17 on the surface of the epitaxial layer 13 from the polysilicon film as the base leading-out electrode 15, and an extrinsic base layer 19 is formed (FIG. 4 (b)).
Furthermore, a polysilicon film is grown on the entire surface. Later, this polysilicon film is etched anisotropically. By this etching, a polysilicon side-wall 20 is formed on the side wall of the polysilicon film 15 as the base leading-out electrode. Using this polysilicon side-wall 20 as mask, the nitride film 18 is removed by etching. Consequently, an emitter leading-out electrode part opening 21 is self-aligned to the polysilicon film as the base leading-out electrode 15 (FIG. 4 (c)).
Finally, a polysilicon film is grown on the entire surface. Then the polysilicon film is etched by using the resist formed by photolithography as mask. As a result, an emitter leading-out electrode 22 is formed. As an impurity, then, boron is implanted into the emitter leading-out electrode 22 by ion implantation. By subsequent heat treatment, the boron is introduced into the intrinsic base region 17 on the surface of the epitaxial layer 13 through the emitter leading-out electrode part opening 21. In this way, an intrinsic base layer 23 is formed. As other impurity, arsenic is implanted into the emitter leading-out electrode 22 by ion implantation. By subsequent heat treatment, the impurity arsenic is introduced into the intrinsic base layer 23 through the emitter leading-out electrode part opening 21. Thus, an emitter layer 24 is formed (FIG. 4 (d)).
In such prior art, emitter leading-out electrode part opening 21 and emitter layer 24 are self-aligned to the base leading-out electrode 15 of polysilicon film. Besides, the intrinsic base layer 23 is formed by diffusing the impurity from the polysilicon film as the emitter leading-out electrode 22. By using such conventional transistor structure, when attempting to integrate ECL circuit or high frequency linear circuit and IIL device on the same substrate, the following problems are involved.
A transistor operating at very high speed is formed by the self-aligned technology, while the IIL device is formed in other process steps. In this case, the number of process steps increases, and therefore the manufacturing cost soars and the production yield drops.
Accordingly, the vertical transistor having the reverse direction structure forming the IIL device must be formed by the self-aligned technology. Beneath the intrinsic base layer which is the emitter of the vertical transistor having the reverse direction structure, the epitaxial layer 13 is formed. The impurity concentration of the epitaxial layer 13 is lower than that of the buried collector layer 12 or intrinsic base layer 23. Therefore, when the thickness of the low impurity concentration region of the epitaxial layer 13 becomes larger, the carrier injection efficiency becomes low, and the current gain is lowered. Hence, the operation of the IIL device becomes unstable.
Or as the thickness of the impurity concentration region increases, the minority carrier accumulates in the epitaxial layer 13 as the emitter layer of the vertical transistor of reverse direction structure. And the minority carrier increases if operating the IIL device. The operating speed of the IIL device is determined by charging or discharging of the minority carrier. As a result, the operation speed of the IIL device declines.
In the light of the above problems, it is hence a primary object of the invention to present a semiconductor integrated circuit having an IIL device capable of operating stably at high speed without increasing the number of process steps or the manufacturing cost.